**Our vision is to transform how the world uses information to enrich life for** **_all_** **.** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. **Our vision is to transform how the world uses information to enrich life for** **_all_** **.** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of a team pushing the boundaries of DRAM verification, where deep circuit knowledge meets modern automation and AI-driven techniques. We work closely with design teams to improve quality, speed, and confidence in silicon. If you enjoy solving hard technical problems and building better ways of working, you'll feel at home here! In this Principal Engineer role, you will be a **technical verification methodology leader** responsible for strengthening DRAM verification quality, standardization, and traceability across project families and pillars-while driving the next generation of **AI-driven verification workflows** and continuously improving scalable verification systems and flows that keep pace with **new products, new features, evolving design methodologies (including shifts toward RTL-centric flows)** , and family-based, scalable product development. This is an ideal role for someone who thrives in ambiguity, enjoys **pathfinding** , and wants to influence how verification is done - not just for one block or one project, but across the DRAM roadmap. **Responsibilities** **Verification Quality and Methodology Governance** + Define and drive DRAM verification quality strategies, including AI-driven methodologies, ensuring verification activities meet high standards for **quality, consistency, traceability, and verification-miss reduction** . + **Drive a closed-loop silicon learning and verification improvement process** by applying core DRAM design and verification expertise to **systematically close silicon failure gaps** and embed the learnings into verification requirements and BKMs to prevent recurrence and reduce the number of DITs and reticles. + Lead end-to-end verification flow analysis for workflow simplification and cycle-time improvements. + Engage with design and verification teams across sites and levels to align on methodology, drive decisions, and communicate tradeoffs as products, features, and design methodologies evolve. **JAMA System Ownership, Improvement, and Scalable Execution** + Own, manage, and evolve the JAMA verification requirements system as the verification standard across project families and pillars. Ensure VE Core Leadership is aligned with updates and improvements through the JAMA notification system. + Ensure requirements, BKMs, and tools remain current and relevant to internal development needs and industry-standard practices. **AI and Pathfinding: Verification Acceleration and Next-Gen Methodology** + Support AI-driven verification initiatives that measurably improve efficiency and effectiveness-including driving automation of requirement decomposition, task generation, coverage-gap detection, failure clustering, debug acceleration, and workflow orchestration. + Define success metrics and converge pilot prototypes into robust, supportable verification workflows. Ensure AI tools integrate safely into engineering practices with strong traceability and quality controls. **Minimum Qualifications:** + Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. + 10+ years of experience in design, verification, or product validation engineering, including DRAM verification and hands‑on work with testbenches, stimulus generation, and failure debug. + Strong expertise in digital and analog design verification concepts and methodologies, with experience developing or applying robust, scalable verification flows. + Solid VLSI fundamentals, including digital logic, semiconductor concepts, and DRAM architecture and operation, with the ability to analyze circuit behavior and translate learnings into improved verification methods. + Excellent communication and collaboration skills, with a proven ability to drive ambiguous, cross‑functional technical problems to closure. + Experience working in a Linux environment and with industry‑standard EDA tools, including Cadence Virtuoso. **Preferred Qualifications:** + Proven ability to define and drive clear, structured, and scalable verification processes or flows across projects or teams. + Experience with requirements management, tracking systems, and structured documentation workflows (e.g., JAMA, JIRA). + Strong analytical skills and attention to detail, with a demonstrated ability to learn and apply new DRAM concepts and verificat