• Support customer’s design through all phases of ASIC execution.
• Ensure designs meet product performance requirements
• Contribute to microarchitecture, RTL design, synthesis, and timing closure.
• Work effectively with internal teams, including verification team and physical design team.
• Tasks may include Architecture / micro-Architecture; Logic Design; RTL integration and coding; Lint/CDC/DFT checks; Synthesis & supporting timing-closure; Contribute to and support Verification; Supporting Firmware and FPGA teams; Silicon bring-up.
• Ensure deadlines for project milestones are met while maintaining quality.

Requirements:

• Bachelor’s Degree in EE or similar degree.
• 5+ years of Front-End ASIC Design experience
• 4+ years of Microarchitecture experience
• Hands-on ASIC front-end design, ideally in design services environments (product backgrounds acceptable).

Preferred:

• Micro-architecture at module/sub-system/chip-level
• Digital design of complex modules/sub-systems, with solid understanding of clock-domain crossings
• Integration of IPs/modules/sub-systems designed by internal/external teams
• Experience using AMBA bus protocols
• System Verilog experience
• Lint and CDC execution and analysis
• Writing timing constraints and timing analysis
• Technical document writing skill
• SoC Architecture experience.
• Experience and domain-knowledge in at least 2-3 of these:
• CPU (preferably, ARM and/or RISC-V), or GPU, or DSP
• SoC Memory hierarchy
• NoC/Fabric
• Low-power design and verification
• high-speed peripheral interfaces such as CSI, HDMI/DP, I3C, USB, PCIe
• Machine-learning / AI
• FPGA